Semiconductor integrated circuits (hereinafter referred to as semiconductor chips) typified by application specific integrated circuits (ASICs) each include a core circuit that processes signals, an input-output circuit that inputs and outputs signals from and to an external circuit, a power supply, and a ground input circuit (GND input circuit). The power supply and the GND input circuit are used by the core circuit and the input-output circuit.
In a typical semiconductor apparatus, the semiconductor chip is installed in a member called a package. Mounting the package having the semiconductor chip installed therein on a print circuit board causes the signal input-output circuit, the power supply, and the GND input circuit in the semiconductor chip to be connected to the print circuit board.
There are many types of packages. When a semiconductor chip having 100 or more input-output terminals is used, for example, a ball grid array (BGA) package is often used. The package such as the BGA package includes a substrate called an interposer and the semiconductor chip is installed on the interposer. The interposer has signal, power, and GND patterns that are wired. The semiconductor chip is connected to the input-output terminals via the wiring.
Since multiple power supplies and multiple GND input circuits for the signal input-output and the core circuit exist in each semiconductor chip in recent years, multiple power patterns and multiple ground patterns exit on the interposer substrate. Accordingly, various measures have been heretofore adopted in order to stabilize the power supply and the grounding.
A method is known in which the power patterns are caused to oppose the GND patterns on the interposer substrate to produce capacitive components between the power patterns and the GND patterns in order to stabilize the power supply and the grounding. U.S. Pat. No. 6,999,299 discloses a technology in which a power plane is divided from a GND plane in the inner layer of the interposer substrate and the power terminals and the GND terminals are alternately arranged to ensure the capacitance.
The current consumption in the semiconductor chip is increased due to miniaturization of a semiconductor process to cause a problem of reduction in direct current (DC) voltage and/or electromigration. Accordingly, it is necessary to build a structure capable of keeping lower impedance and causing a large amount of current to flow by decreasing the resistances of the power patterns and the GND patterns in the semiconductor apparatus and the print circuit board.
In addition, the increase in the current consumption in the semiconductor chip promotes use of many power supplies in the semiconductor chip. For example, the power supply of the semiconductor chip is divided into multiple power supplies to stop some of the circuits during the operation or to supply lower voltage to circuits having lower operation frequencies. Consequently, the power patterns and the GND patterns in the semiconductor apparatus are required to have a structure that is easy to support the many power supplies in the semiconductor chip. However, many via holes for different voltages exist in the respective power and GND areas (for example, many GND via holes and many power via holes for different voltages exist in the power area) in the method in the related art, typified by the technology disclosed in U.S. Pat. No. 6,999,299, in which many via holes for the power supply and the grounding are closely arranged. Accordingly, the effective resistance is practically increased due to the many through holes even if the plane shape is adopted in order to reduce the resistance to prevent the impedance from being kept at a lower value.